The Qualcomm Atheros AR9582 is a highly integrated single-chip solution for 5 GHz 802.11n wireless local area networks (WLANs) that enables high-performance 2x2 MIMO with 2 Spatial Streams for wireless applications demanding the highest robust link quality and maximum throughput and range. The AR9582 integrates a multi-protocol MAC, baseband processor, analogto- digital/digital-to-analog converters (ADC/DAC), 2x2 MIMO radio transceivers, and PCI Express interface in an all-CMOS device for low power consumption and small form-factor applications. The AR9582 implements half-duplex OFDM, CCK, and DSSS baseband process, supporting up to 150 Mbps for 20 MHz and 300 Mbps for 40 MHz channel operations, and IEEE 802.11a/b/g data rates. Additional features include Maximal Likelihood (ML) decoding, Low-Density Parity Check (LDPC), Maximal Ratio Combining (MRC), Tx Beamforming (TxBF), Space Time Block Code (STBC), and On-Chip One-Time Programmable (OTP) memory. The AR9582 supports 802.11 wireless MAC protocol, 802.11i security, Rx/Tx filtering, error recovery, and 802.11e quality of service (QoS). The AR9582 supports up to two simultaneous traffic streams integrating two Tx and two Rx chains for high throughput and extended coverage. Tx chains combine baseband in-phase (I) and quadrature (Q) signals, convert them to the desired frequency, and drive the RF signal to multiple antennas. Rx chains use an integrated architecture. The frequency synthesizer supports 1-MHz steps to match frequencies defined by IEEE 802.11a/ g/n specifications. The AR9582 supports frame data transfer to and from the host using a PCIE interface providing interrupt generation and reporting, power save, and status reporting. Other external interfaces include EEPROM.
Dynamic frequency selection (DFS) in required 5-GHz bands when used as an AP 2x2 MIMO technology improves effective throughput and range over existing 802.11a/n products Supports spatial multiplexing, cyclic-delay diversity (CDD), low-density parity check (LDPC), maximal ratio combining (MRC), Space Time Block Code (STBC), and Tx Beamforming (TxBF)
Smart antenna diversity Single-ended RF ports with integrated matching simplify board design and layout Integrated 1.2 V switching regulator Data rates of up to 150Mbps for 20 MHz channels and 300 Mbps for 40 MHz channels using reduced (short) guard interval On-Chip One-Time Programmable memory Support for IEEE 802.11e, h, and i standards WEP, TKIP, AES, and WAPI hardware encryption PCI Express 1.1 interface 20 and 40 MHz channelization High Tx power accuracy at lower power level 8 bits spectral analysis resolution Frame aggregation, block ACK 802.11e-compatible bursting Support for 2/3/4/6-wire BT coexistence